cirrus logic er633a1 www.cirrus.com/ oct ?04 1 copyright ? cirrus logic, inc. 2004 (all rights reserved) 10/7/2004 errata: CS44600 rev. a rev. a silicon (reference CS44600 datasheet revision ds633a3) ? in spi control port mode, during write operations, the cdout pin does not stay in the hi-z state, but instead drives high or low. this is not a concern for systems where the CS44600 is the only slave device on the spi bus. however, this will cause bus contention in systems where the cdout signal is shared between multiple slave devices. this will operate as per the datasheet in rev b. i2c control port mode operates as stated in the datasheet. ? when gpio[3:0] are configured as edge trigger inputs (as set in the gpio pin level/edge trigger register, address 2eh) and an edge event occurs, the gpio status will not be cleared after a read of the gpio status register (address 2fh) unless the affected gpio has had its interrupt unmasked (as set in the gpio interrupt mask register, address 30h). therefore, if edge sensitivity is needed for gpio[3:0], the corresponding interrupt should be unmasked, regardless if interrupts are being used. gpio[6:4] operate as described in the data sheet. this will operate as per the datasheet in rev b. ? when the minimum pwm output pulse width is set to a non-zero value (as set in the minimum pwm output pulse width regist er, address 32h), the power down output mode is set to 1 (as set in the clock configuration and power control register, address 02h), and the pwm channel is powered down (as set in the pwm channel power down control register, address 03h), pulses will be output on the powered down channel?s inverted output (pwmoutxx-). the pulse width will be equivalent to the min_pulse[4:0] setting. power down output is correct if the minimum pwm output pulse width is set to 0 or the power down output mode is set to 0. this will operate as per the datasheet in rev b. ? the inverted pwm outputs (pwmoutxx-) can go low at the beginning of a ramp-up sequence regardless of the power down output mode setting (as set in the clock configuration and power control register, address 02h). this will operate as per the datasheet in rev b.
2 er633a1 ? the channel output configuration bits (a1/b1_out_cnfg, a2/b2_out_cnfg, a3_out_cnfg, and b3_out_cnfg) in th e pwm configuration register (address 31h) work as defined in the datasheet for psr feedback, however these bits are transposed for ramp-up/down functionality. therefore, these bits should all be set to the same value. this will operate as per the datasheet in rev b. ? it is not recommended to continuously read (poll) the interrupt status register (address 2ah) for updates. continued read operations to the interrupt status register may cause an invalid event status to be reported. the recommended method to check event status is to enable the register bits to generate an interrupt (using the interrupt mode control register, address 28h, and the interrupt mask register, address 29h). once the interrupt has been issued by the CS44600 to the host controller, perform a read operation to the interrupt status register. this will operate as per the datasheet in rev b. ? when using the internal oscillator, performance is degraded as compared to using an external clock source. this will operate as per the datasheet in rev b. ? the CS44600 rev a meets the jesd22-114 (human body model) and jesd22-115 (machine model) specifications for esd. however, for proper operation, the voltage used for the control port (vlc) must be set to a maximum of 2.5 v. a level shifter must be used to interface 3.3 v or 5.0 v control logic with the CS44600 rev a control port operating at 2.5 v. this will operate as per the datasheet in rev b. contacting cirrus logic support for all product questions and inquiries cont act a cirrus logic sales representative. to find one nearest you go to http://www.cirrus.com/
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